The Cement Shortage Nobody Reported: How AI Absorbed the Semiconductor Industry's Marginal Capacity

When One Buyer Rents Every Crane in the City

Imagine a mid-sized city where every crane, cement mixer and licensed electrician is suddenly contracted to a single stadium project. The stadium rises on schedule. The housing, the clinic extension and the bridge repairs quietly slip, and a bag of cement doubles in price — not because cement became scarce, but because attention did. That is the semiconductor market's present condition. AI accelerator demand has absorbed the industry's marginal wafer, packaging and test capacity, and the cost of that absorption is being paid by every buyer who is not purchasing an accelerator. Five developments — memory reallocation, back-end congestion, High-NA capital intensity, fab geography and materials statecraft — are now compounding into one structural event rather than five separate ones.

The Back End Is the New Front End

Mainstream coverage still ranks the industry by nanometres. That taxonomy is obsolete. An accelerator is not a die; it is a die, eight to twelve HBM stacks, an interposer, a substrate and a thermal solution, assembled and tested in sequence. Wafer fabrication can be ahead of schedule while the product ships late because the interposer line is full. This relocates pricing power downstream to OSATs and substrate suppliers who spent two decades as low-margin subcontractors, and it changes what a capacity announcement actually means. When a government celebrates a fab groundbreaking, it is funding the part of the chain that is no longer binding. The binding constraint sits in packaging and final test — capital-light by comparison, slower to permit, and concentrated in fewer jurisdictions than lithography ever was.

Sovereignty Has a Price — and the Invoice Is Contested

The counter-case to the de-globalisation critique deserves a fair hearing. The standard argument treats geographic diversification as pure deadweight loss, and it leans heavily on a single data point: Morris Chang, speaking at the Brookings Institution in April 2022, estimated US chip manufacturing costs at roughly 50% above Taiwan's, later suggesting he had understated it. That figure is real, but it is a 2022 estimate made before a single Arizona line reached volume, before supplier clusters formed, and before the learning curve bent. First-of-a-kind fabs are always expensive; nth-of-a-kind fabs are not. TSMC has guided to overseas dilution in the low single digits of gross margin, not fifty percent. More decisively, customers have begun paying the premium voluntarily. Reshoring is better modelled as an insurance premium with a measurable strike price than as waste — and insurance is only overpriced until the year it pays out.

Leverage Decays: Tokyo, 2019

The closest precedent is not the 2021 automotive shortage. It is Japan's July 2019 restriction on photoresist, hydrogen fluoride and fluorinated polyimide exports to South Korea. Tokyo controlled overwhelming share in three narrow inputs and expected rapid capitulation. Instead, Seoul funded qualification programmes, Samsung and SK hynix certified alternative suppliers within roughly twelve months, and Japan withdrew the measures in March 2023 with its leverage substantially spent. The Nexperia episode repeated the pattern in miniature: a single packaging node became a continental production risk, and the response was immediate dual-sourcing. The lesson is a decay function. Chokepoint power is a depreciating asset whose half-life is set by the buyer's qualification cycle — typically eighteen to thirty-six months in chemicals, longer in tools. Each invocation converts a commercial dependency into a funded national substitution programme.

The Physics Bill Arrives Before the Lithography Bill

The second under-covered implication is that the industry's constraint is migrating from capital to electricity. The IEA's Energy and AI report (April 2025) put global data-centre consumption at approximately 415 TWh in 2024, projecting roughly 945 TWh by 2030 — a doubling that grid interconnection queues, not fab shells, will govern. This inverts a thirty-year assumption. Process shrinks were sold on performance-per-watt; they are now sold on performance-per-available-watt, which is a different optimisation entirely. It advantages architectures with superior memory-bandwidth-per-joule over those with superior peak FLOPS, and it makes trailing-node efficiency work commercially rational again. A chip that cannot be powered is inventory, not revenue.

The Control Illusion

A second counter-argument is warranted against the assumption that export controls are decisive. Restrictions imposed since October 2022 measurably slowed Chinese access to leading-edge tooling — that is not seriously disputed. But they also created a guaranteed, state-underwritten domestic market for Chinese equipment and memory makers, and accelerated the very substitution they were designed to postpone. Nor is demand obedient to jurisdiction. Jensen Huang, at the World Governments Summit in February 2024, argued that every country needs to "own the production of their own intelligence" — a framing that has since justified sovereign compute budgets on four continents. Controls calibrated for a bipolar market are being applied to a multipolar one. The realistic objective is delay measured in node-generations, not denial, and policy that promises the latter will be judged against an unachievable benchmark.

Node Inflation and the Squeeze on Everyone Else

The third implication lands on industrial, medical and automotive buyers who will never purchase an accelerator. As HBM absorbs DRAM starts and packaging absorbs capital, mature-node and commodity memory buyers lose allocation priority without losing contractual obligations. Simultaneously, leading-edge design costs push all but a handful of firms toward chiplets and licensed IP, concentrating architectural decision-making in fewer hands. Deloitte's semiconductor outlook has projected the industry needs more than one million additional skilled workers by 2030 — a shortfall concentrated precisely in the process, packaging and test engineering roles that this transition demands. The talent constraint and the capacity constraint are the same constraint wearing two labels.

What to Do Before the Next Allocation Letter

• Re-underwrite BOM risk at the packaging layer. Ask suppliers where interposer, substrate and final-test capacity sits — not where the wafer is fabbed. Single-site packaging exposure is the Nexperia risk, and it is auditable today.
• Convert spot exposure into dated commitments. For commodity DRAM and mature-node parts, secure long-term agreements with volume floors while allocation leverage still favours buyers with credible forecasts.
• Qualify a second source now, while it is optional. Qualification takes quarters. Beginning it during a shortage means finishing it after the margin is gone.
• Price power before silicon. Any deployment plan without a secured interconnection date is a forecast, not a plan.
• Fund packaging and test engineering, not only design. That is where the scarcity — and the salary arbitrage — now sits.

May 2027: Three Prices for the Same Wafer

Six months out, expect a market that has stopped pretending capacity is fungible. First, a visible price hierarchy: AI-allocated, sovereignty-allocated and commercial-allocated output will trade at distinguishable premiums for functionally similar silicon. Second, expect packaging and substrate vendors to capture disproportionate margin and to become acquisition targets, with at least one major vertical integration attempt by a systems company. Third, expect memory to remain the tightest link, because HBM's wafer-per-bit penalty is structural, not cyclical. What will not normalise is the assumption underneath the last decade of procurement: that any buyer with money can obtain any part in thirteen weeks. The stadium is still being built. The rest of the city has learned to schedule around it.